1. Field of the Invention
The present invention relates to a master-slave S/R flip-flop circuit wherein the master stage employs capacitive storage to establish its logic state, and particularly to such a flip-flop wherein the master stage is coupled to the slave stage by an interstage coupling comprising a combination of field effect transistors (referred to herein as "FET devices") and bipolar transistors.
2. Description of the Related Art
Flip-flop circuits are an essential element of digital storage registers and memories, being capable of being switched from one to another logic state in response to a data pulse and then returned to the initial state in response to a reset pulse. Such circuits are generally clocked so that switching occurs at a rising or falling edge of an accurately timed clock pulse, such a clocked flip-flop being generally referred to as an S/R (Set/Reset) flip-flop. In order to assure that a change in input conditions occurring during the clock pulse does not produce an unpredictable result the flip-flop may comprise two stages, an input master stage and an output slave stage, the pulse being stored in the master stage and then transferred to the slave stage upon occurrence of the clock pulse. In this way the slave stage is isolated from transient changes in input conditions, thereby improving the reliability of the S/R flip-flop.
Each stage typically comprises a pair of cross-coupled logic gates, such as NAND gates or NOR gates, together with a pair of AND or NAND gates to provide clocked operation. Consequently, it is evident that a dual stage master-slave S/R flip-flop will involve considerable circuit complexity and power consumption. Considerable effort has therefore been devoted to simplifying the design of such flip-flops.
U.S. Pat. No. 3,812,388, issued May 21, 1974, discloses a dual-stage S/R flip-flop wherein in lieu of cross-coupled logic gates the input flip-flop employs the gate capacitance of each of a pair of FET devices to store an input set pulse as well as the subsequent reset pulse. However, in order to obtain clocked operation two different sequences of clock signals in interleaved phase relationship are required. U.S. Pat. No. 3,624,423, issued Nov. 30, 1971, discloses a clocked S/R flip-flop wherein the gate capacitance of each of a pair of FET devices, which control set and reset, are employed to store alternately positive and inverted clock pulse sequences. Again, two different clock pulse sequences must be provided. The article "D-type Latch" by Puri et al, IBM Tech. Bulletin, vol. 24, No. 8, January 1982, discloses a single stage clocked flip-flop wherein the gate capacitance of an input FET is employed to store an input data pulse and transfer it to the gate capacitance of an output FET upon occurrence of a falling edge of a clock pulse. However, such circuit does not assure stabilization of the state of the flip-flop against possible changes at the data input during a falling edge of the clock pulse.
Such prior art S/R flip-flops employ either all FET devices or all bipolar transistors, each of which technologies have advantages and disadvantages. Bipolar achieves higher speed operation, but is more complex and has relatively high power consumption. FET circuits implemented in CMOS achieve low power consumption but also have a lower operating speed. Applicants have perceived that it is possible to combine both technologies in a manner which achieves both high speed and low power consumption as well as reduced layout area on an LSI chip, and the present invention combines FET devices and bipolar transistors to provide interstage coupling of the master and slave stages.